{"items":[{"layer_id":"eda-ip","eyebrow":"01 / The executable blueprint","title":"A chip is debugged in software before it becomes geometry.","description":"Architecture becomes register-transfer logic, reusable IP, a gate-level netlist, placed-and-routed geometry, and finally a verified tape-out package. Each handoff constrains power, performance, area, schedule, and manufacturability before a foundry touches a wafer.","input":"Workload requirements · architecture · foundry design rules","output":"Verified layout database · masks-ready tape-out · embedded IP licenses","economic_unit":"EDA subscription · IP license/royalty · engineering seat · tape-out","bottlenecks":["Verification closure","Timing and power closure","Foundry-qualified IP","Engineering schedule","Mask re-spin risk"],"components":[{"component_id":"eda-ip:architecture","label":"Architecture + RTL","category":"Logical intent","description":"System requirements are partitioned into compute, memory, I/O, control, and security blocks, then expressed as hardware behavior in RTL.","economic_unit":"engineer-month · design block","what_to_watch":"Watch whether the architecture can meet bandwidth and power targets before implementation complexity hardens.","metrics":[{"label":"Input","value":"workload + constraints"},{"label":"Output","value":"RTL + block plan"}],"source_id":"src_synopsys_eda_flow"},{"component_id":"eda-ip:ip","label":"Reusable IP","category":"Licensed building blocks","description":"Processor cores, memory controllers, SerDes, PCIe, die-to-die links, and standard-cell libraries let design teams reuse silicon-proven functions instead of rebuilding every interface.","economic_unit":"license · royalty · instantiated block","what_to_watch":"Foundry-node qualification, interface standards, and verification collateral determine whether reusable IP actually shortens the schedule.","metrics":[{"label":"Examples","value":"CPU · SerDes · PHY"},{"label":"Gate","value":"node qualification"}],"source_id":"src_tsmc_hpc_platform"},{"component_id":"eda-ip:synthesis","label":"Logic synthesis","category":"RTL to gates","description":"Synthesis converts RTL into a gate-level netlist using foundry libraries while optimizing for timing, power, area, and testability.","economic_unit":"synthesis run · compute hour","what_to_watch":"Constraint quality matters: a netlist can be logically correct yet impossible to close physically at the target clock or power envelope.","metrics":[{"label":"Input","value":"RTL + libraries"},{"label":"Output","value":"gate netlist"}],"source_id":"src_synopsys_eda_flow"},{"component_id":"eda-ip:physical","label":"Place + route","category":"Physical implementation","description":"Billions of gates are positioned and their metal connections routed while tools resolve congestion, clocking, power delivery, thermal density, and design rules.","economic_unit":"design iteration · EDA compute","what_to_watch":"Routing congestion and timing violations often force architectural or floorplan changes late in the cycle, when delay is expensive.","metrics":[{"label":"Optimizes","value":"power · performance · area"},{"label":"Output","value":"physical layout"}],"source_id":"src_synopsys_eda_flow"},{"component_id":"eda-ip:signoff","label":"Verification + signoff","category":"Risk retirement","description":"Simulation, formal checks, timing analysis, power analysis, and layout-versus-schematic checks establish that the implemented design behaves as intended and can be manufactured.","economic_unit":"verification cycle · coverage target","what_to_watch":"Coverage gaps and late-found violations create re-spins. First-pass silicon is a schedule and capital event, not only a technical milestone.","metrics":[{"label":"Checks","value":"function · timing · power"},{"label":"Decision","value":"tape-out"}],"source_id":"src_synopsys_eda_flow"}],"example":{"title":"From RTL to a manufacturable layout","description":"Synopsys' official EDA overview connects logic synthesis, digital place-and-route, verification, validation, and silicon correlation. The important economic point is the iteration loop: errors caught in software avoid a mask re-spin and lost fab time.","metrics":[{"label":"Flow","value":"RTL → gates → layout"},{"label":"Closure","value":"timing · power · function"},{"label":"Release gate","value":"signoff"}],"company_ids":["cmp_synopsys","cmp_cadence"],"source_id":"src_synopsys_eda_flow"}},{"layer_id":"chip-network-design","eyebrow":"02 / The system architecture","title":"The accelerator is only useful when compute, memory, and fabric stay in balance.","description":"Chip and network designers decide the math engines, on-package memory interfaces, host links, scale-up domain, scale-out fabric, and software-visible topology. Useful AI throughput depends on feeding the arithmetic units and coordinating many devices, not peak FLOPS alone.","input":"Model behavior · latency target · power envelope · available process and packaging","output":"Accelerator, switch, NIC, DPU, and fabric designs ready for tape-out","economic_unit":"chip · board · port · bandwidth · rack-scale system","bottlenecks":["Memory bandwidth","All-to-all communication","SerDes reach and power","Software collectives","Package and reticle limits"],"components":[{"component_id":"chip-network-design:compute","label":"Compute engines","category":"Accelerator die","description":"Tensor, vector, scalar, and control engines execute the model while cache and scheduling logic try to keep the datapaths occupied.","economic_unit":"accelerator · FLOPS · tokens/s","what_to_watch":"Compare delivered workload throughput and utilization, not incompatible peak-precision claims.","metrics":[{"label":"Unit","value":"accelerator"},{"label":"Outcome","value":"useful throughput"}],"source_id":"src_nvidia_nvlink_architecture"},{"component_id":"chip-network-design:memory-interface","label":"Memory controllers","category":"Data movement","description":"HBM controllers and PHYs move weights, activations, and key-value cache between stacked memory and the compute die over a very wide interface.","economic_unit":"GB/s · TB/s · pJ/bit","what_to_watch":"Capacity, bandwidth, and energy per bit can each become the binding constraint for a different model or serving regime.","metrics":[{"label":"Path","value":"HBM ↔ compute"},{"label":"Watch","value":"bandwidth utilization"}],"source_id":"src_micron_hbm_overview"},{"component_id":"chip-network-design:scale-up","label":"Scale-up fabric","category":"Inside the accelerator domain","description":"High-bandwidth links and switch silicon join GPUs within a server or rack so collective operations can treat the domain as a tightly coupled compute unit.","economic_unit":"GB/s per GPU · domain size","what_to_watch":"Topology, oversubscription, latency, and collective efficiency determine how much of link bandwidth becomes model throughput.","metrics":[{"label":"Blackwell NVLink","value":"1,800 GB/s per GPU"},{"label":"Domain","value":"up to 72 GPUs"}],"source_id":"src_nvidia_nvlink_architecture"},{"component_id":"chip-network-design:scale-out","label":"Scale-out fabric","category":"Across racks","description":"NICs, DPUs, Ethernet or InfiniBand switches, optics, and routing connect accelerator domains to one another and to storage.","economic_unit":"Gb/s per port · radix · network tier","what_to_watch":"Tail latency, congestion control, optical reach, and failure domains become more important as cluster size grows.","metrics":[{"label":"Traffic","value":"east/west collectives"},{"label":"Boundary","value":"rack → cluster"}],"source_id":"src_nvidia_nvlink_architecture"},{"component_id":"chip-network-design:software","label":"Collectives + control","category":"System software","description":"Drivers, communication libraries, topology discovery, and switch control turn physical links into usable all-reduce, broadcast, partitioning, and fault recovery.","economic_unit":"job goodput · availability","what_to_watch":"A fast fabric with poor topology awareness or resiliency strands accelerator time. Watch delivered job completion, not link rate alone.","metrics":[{"label":"Operations","value":"reduce · broadcast"},{"label":"Outcome","value":"cluster goodput"}],"source_id":"src_nvidia_nvlink_architecture"}],"example":{"title":"GB300 NVL72: one design spans die, link, switch, and rack","description":"NVIDIA documents fifth-generation NVLink at up to 1,800 GB/s per GPU and a 72-GPU rack domain. That is the architectural lesson: accelerator silicon and network silicon are co-designed as one performance envelope.","metrics":[{"label":"GPUs","value":"72"},{"label":"Per-GPU link","value":"1,800 GB/s"},{"label":"Switch trays","value":"9"}],"company_ids":["cmp_nvidia","cmp_broadcom","cmp_marvell"],"source_id":"src_nvidia_nvlink_architecture"}},{"layer_id":"materials","eyebrow":"03 / The purity stack","title":"Every patterned layer begins with materials clean enough not to become defects.","description":"A polished silicon wafer is only the substrate. Photoresists, masks, deposition precursors, process gases, wet chemicals, slurries, filtration, and wafer handling enter repeatedly as the device is built layer by layer. Consistency and contamination control are yield inputs.","input":"Electronic-grade polysilicon · gases · chemicals · metals · polymers","output":"Prime wafers and process materials delivered to exact purity and geometry specifications","economic_unit":"wafer · liter · kilogram · cylinder · defect density","bottlenecks":["Purity","Particle and metal contamination","Wafer flatness","Precursor consistency","Single-source qualification"],"components":[{"component_id":"materials:crystal","label":"Single-crystal ingot","category":"Silicon foundation","description":"Electronic-grade polysilicon is melted and a single-crystal ingot is pulled so the wafer begins with a controlled atomic structure and resistivity.","economic_unit":"kilogram · ingot · crystal yield","what_to_watch":"Crystal defects and resistivity variation propagate through every later process; qualification cycles make supplier changes slow.","metrics":[{"label":"Method","value":"CZ crystal growth"},{"label":"Output","value":"monocrystalline ingot"}],"source_id":"src_sumco_wafer_process"},{"component_id":"materials:wafer","label":"Prime silicon wafer","category":"Substrate geometry","description":"The ingot is sliced, lapped, chemically etched, polished to a mirror finish, cleaned, and inspected before it can enter a leading-edge fab.","economic_unit":"300 mm wafer · flatness · particles","what_to_watch":"Bow, warp, surface particles, and crystal defects affect focus, overlay, and downstream yield.","metrics":[{"label":"Forming steps","value":"5"},{"label":"Finish","value":"mirror-polished"}],"source_id":"src_sumco_wafer_process"},{"component_id":"materials:resist-mask","label":"Resist + mask materials","category":"Pattern transfer","description":"Photoresist changes chemically under exposure while reticles carry the pattern. Developers, underlayers, pellicles, and cleaning materials support each lithography cycle.","economic_unit":"wafer pass · reticle · liters of chemical","what_to_watch":"Stochastic defects, line-edge roughness, shelf life, and contamination determine whether the printed pattern survives transfer.","metrics":[{"label":"Role","value":"light → pattern"},{"label":"Loop","value":"coat · expose · develop"}],"source_id":"src_asml_chipmaking_process"},{"component_id":"materials:precursors","label":"Gases + precursors","category":"Film and feature chemistry","description":"Ultra-high-purity precursors create conductive, insulating, and semiconductor films; reactive gases selectively remove material during etch.","economic_unit":"cylinder · kilogram · wafer pass","what_to_watch":"Purity, delivery stability, chamber compatibility, and residue control affect film uniformity and device reliability.","metrics":[{"label":"Deposition","value":"ALD · CVD films"},{"label":"Risk","value":"particles · metals · organics"}],"source_id":"src_entegris_deposition_materials"},{"component_id":"materials:contamination","label":"Filtration + handling","category":"Contamination control","description":"Filters, purifiers, wafer carriers, coatings, and cleanroom systems keep particles and trace metals out of materials and process chambers.","economic_unit":"particles per volume · filter life","what_to_watch":"At advanced geometries, contaminants smaller than a visible speck can kill a die; monitor purity at delivery and at point of use.","metrics":[{"label":"Control","value":"filter · purify · contain"},{"label":"Outcome","value":"fewer defects"}],"source_id":"src_entegris_deposition_materials"}],"example":{"title":"A polished wafer already contains a supply chain","description":"SUMCO shows five controlled wafer-forming stages after crystal growth—slicing, lapping, etching, polishing, then cleaning and inspection. The fab buys a precisely qualified surface, not a generic disc of silicon.","metrics":[{"label":"Wafer forming","value":"5 stages"},{"label":"Starting slice","value":"about 1 mm"},{"label":"Release","value":"clean + inspect"}],"company_ids":["cmp_sumco","cmp_shin-etsu-chemical","cmp_entegris"],"source_id":"src_sumco_wafer_process"}},{"layer_id":"wafer-fab-equipment","eyebrow":"04 / The process loop","title":"A fab repeats deposition, patterning, etch, and measurement until a device emerges.","description":"Leading-edge manufacturing is not one machine. Tool families add films, print patterns, remove material, alter electrical properties, clean surfaces, and measure the result. Data from inspection and metrology feeds the next adjustment, while uptime and throughput govern factory economics.","input":"Prime wafer · reticle · process recipe · gases and chemicals","output":"Patterned wafer with stacked transistor and interconnect layers","economic_unit":"tool · wafer pass · wafers/hour · uptime · installed base service","bottlenecks":["EUV availability","Process uniformity","Chamber uptime","Overlay and critical dimensions","Defect detection sensitivity"],"components":[{"component_id":"wafer-fab-equipment:deposition","label":"Deposition","category":"Add material","description":"CVD, PVD, and ALD tools deposit conductors, insulators, and semiconductor films with atomic-scale thickness and uniformity control.","economic_unit":"wafer pass · film thickness · wafers/hour","what_to_watch":"Uniformity, precursor use, chamber matching, and particle generation determine whether the next patterning step starts from a stable film.","metrics":[{"label":"Action","value":"add a thin film"},{"label":"Control","value":"thickness + uniformity"}],"source_id":"src_asml_chipmaking_process"},{"component_id":"wafer-fab-equipment:lithography","label":"Lithography","category":"Print the pattern","description":"DUV and EUV scanners project a reticle pattern onto photoresist. Resolution, overlay, focus, source power, and tool availability set the patterning envelope.","economic_unit":"wafer pass · wafer/hour · overlay","what_to_watch":"Critical layers depend on scarce, complex systems. Throughput and uptime can matter as much as nominal resolution.","metrics":[{"label":"Critical input","value":"light + reticle"},{"label":"Output","value":"patterned resist"}],"source_id":"src_asml_lithography_principles"},{"component_id":"wafer-fab-equipment:etch","label":"Etch + clean","category":"Remove material","description":"Plasma and wet processes remove exposed material while preserving masked regions; cleans strip residue before the next layer.","economic_unit":"wafer pass · selectivity · etch rate","what_to_watch":"Profile control, chamber condition, residues, and damage are tightly coupled to yield on dense three-dimensional structures.","metrics":[{"label":"Action","value":"remove exposed material"},{"label":"Risk","value":"profile + residue"}],"source_id":"src_asml_chipmaking_process"},{"component_id":"wafer-fab-equipment:implant-cmp","label":"Implant + planarize","category":"Tune and reset","description":"Ion implantation changes electrical properties; chemical-mechanical polishing flattens the surface so another precisely aligned layer can be built.","economic_unit":"dose · wafer pass · removal rate","what_to_watch":"Dose uniformity and surface planarity must stay within a shrinking process window across the full wafer.","metrics":[{"label":"Implant","value":"tune conductivity"},{"label":"CMP","value":"restore flatness"}],"source_id":"src_asml_chipmaking_process"},{"component_id":"wafer-fab-equipment:metrology","label":"Metrology + inspection","category":"Close the loop","description":"Optical and electron-beam systems measure dimensions and overlay, find defects, and classify excursions so recipes or tools can be corrected before more value is added.","economic_unit":"inspection pass · sampling rate · defect density","what_to_watch":"Sensitivity competes with throughput. Sampling plans must find systematic defects without turning process control into the line bottleneck.","metrics":[{"label":"Inspection","value":"find defects"},{"label":"Metrology","value":"measure precision"},{"label":"Feedback","value":"recipe correction"}],"source_id":"src_kla_process_control"}],"example":{"title":"One layer is a loop; a chip can repeat it up to 100 times","description":"ASML's manufacturing explainer traces deposition, photoresist, exposure, development, etch, implantation, resist removal, and measurement. Repetition makes uptime, repeatability, and process-control feedback central to fab output.","metrics":[{"label":"Front-end flow","value":"hundreds of steps"},{"label":"Layer loop","value":"up to 100 repeats"},{"label":"Feedback","value":"metrology → equipment"}],"company_ids":["cmp_asml","cmp_applied-materials","cmp_lam-research","cmp_kla"],"source_id":"src_asml_chipmaking_process"}},{"layer_id":"foundries-idms","eyebrow":"05 / The yield factory","title":"The foundry converts a design file into repeatable, qualified good die.","description":"After tape-out, masks and process recipes send wafer lots through hundreds of front-end steps. A foundry or IDM manages cycle time, equipment availability, process control, yield learning, customer qualification, and volume ramp across a technology platform.","input":"Signed-off layout · mask set · process design kit · wafer starts","output":"Tested wafer · known-good logic die · qualified production capacity","economic_unit":"wafer start · wafer/month · good die · yield · process node","bottlenecks":["Yield ramp","Cycle time","Qualified wafer capacity","Mask and process readiness","Customer concentration and allocation"],"components":[{"component_id":"foundries-idms:tapeout","label":"Tape-out + masks","category":"Customer handoff","description":"The signed-off layout is fractured into mask data and checked against foundry rules before production reticles are released.","economic_unit":"mask set · tape-out · NRE","what_to_watch":"Mask cost and queue time make late design changes expensive; first-pass success protects both schedule and wafer capacity.","metrics":[{"label":"Input","value":"verified layout"},{"label":"Release","value":"mask set"}],"source_id":"src_tsmc_foundry_services"},{"component_id":"foundries-idms:wafer-start","label":"Wafer starts","category":"Factory capacity","description":"A wafer lot is introduced to the line and routed through the qualified process flow, repeatedly visiting tool groups over months.","economic_unit":"wafer starts/month · lot","what_to_watch":"Announced shell capacity is not the same as installed, qualified, and customer-allocated wafer starts.","metrics":[{"label":"Unit","value":"300 mm wafer start"},{"label":"State","value":"installed → qualified"}],"source_id":"src_asml_chipmaking_process"},{"component_id":"foundries-idms:process","label":"Process integration","category":"Recipe coherence","description":"Transistor, interconnect, patterning, materials, and thermal steps must work as one reproducible process rather than as isolated tool recipes.","economic_unit":"process node · design rule · recipe","what_to_watch":"A nominal node label does not reveal performance, density, yield, or customer readiness; watch qualified products and volume state.","metrics":[{"label":"Scope","value":"transistor → interconnect"},{"label":"Artifact","value":"qualified flow"}],"source_id":"src_tsmc_hpc_platform"},{"component_id":"foundries-idms:yield","label":"Yield learning","category":"Good die conversion","description":"Inspection, electrical test, failure analysis, and statistical process control identify defect mechanisms and raise the share of dies that meet specification.","economic_unit":"good die/wafer · defect density","what_to_watch":"Yield on a large accelerator die can dominate delivered cost and volume. Early ramps should not be treated like mature output.","metrics":[{"label":"Input","value":"patterned wafer"},{"label":"Output","value":"good die"}],"source_id":"src_kla_process_control"},{"component_id":"foundries-idms:ramp","label":"Qualification + ramp","category":"Commercial release","description":"Process reliability, package interaction, product test, and customer signoff convert engineering lots into repeatable high-volume shipments.","economic_unit":"qualified product · ramp quarter","what_to_watch":"Expected operation dates, risk production, qualification, and volume production are different milestones and should remain distinct.","metrics":[{"label":"Milestones","value":"risk → qualify → volume"},{"label":"Evidence","value":"company + government"}],"source_id":"src_nist_tsmc_arizona"}],"example":{"title":"TSMC Arizona Fab 1: operation is a state, not an announcement","description":"The NIST project record distinguishes construction, production milestones, technology scope, and program commitments. Semiconductor capacity becomes economically relevant only after tools, process, yield, and customer qualification converge.","metrics":[{"label":"Technology","value":"N4"},{"label":"Wafer","value":"300 mm"},{"label":"State","value":"operational"}],"company_ids":["cmp_tsmc","cmp_intel","cmp_samsung-electronics"],"source_id":"src_nist_tsmc_arizona"}},{"layer_id":"hbm-memory","eyebrow":"06 / The bandwidth wall","title":"HBM moves memory beside compute and widens the road between them.","description":"High-bandwidth memory stacks DRAM dies vertically, connects them with through-silicon vias and microbumps, and places the stack beside logic on an interposer. Capacity, bandwidth, thermals, stack yield, and packaging availability now shape accelerator output.","input":"DRAM wafer · base die · TSV process · known-good dies","output":"Qualified HBM stack integrated beside an accelerator","economic_unit":"stack · gigabyte · TB/s · energy/bit · known-good die","bottlenecks":["DRAM die yield","TSV and microbump yield","Stack height","Thermal envelope","Packaging co-capacity"],"components":[{"component_id":"hbm-memory:dram-die","label":"DRAM dies","category":"Memory cells","description":"Multiple DRAM dies supply the capacity and parallel channels. Each layer must be tested because one weak die can compromise the stack.","economic_unit":"gigabit die · known-good die","what_to_watch":"Bit density, process yield, speed grade, and power all affect how many stackable dies emerge from a wafer.","metrics":[{"label":"Role","value":"store model state"},{"label":"Gate","value":"known-good die"}],"source_id":"src_micron_hbm_overview"},{"component_id":"hbm-memory:tsv","label":"TSVs + microbumps","category":"Vertical interconnect","description":"Thousands of vertical vias and fine-pitch bonds carry data, power, and control through the stack over much shorter paths than a conventional module.","economic_unit":"via · microbump · bond pitch","what_to_watch":"Via defects, bond alignment, and thermal stress compound across stacked dies.","metrics":[{"label":"Direction","value":"vertical"},{"label":"Scale","value":"thousands of TSVs"}],"source_id":"src_micron_hbm_overview"},{"component_id":"hbm-memory:base-die","label":"Base die + channels","category":"Stack control","description":"An optional base die and channel architecture organize the ultra-wide interface and connect the stack to package routing.","economic_unit":"channel · I/O width","what_to_watch":"Controller compatibility and channel utilization determine whether headline bandwidth is reachable by the workload.","metrics":[{"label":"Micron example","value":"32 channels"},{"label":"Interface","value":"1,024 bits"}],"source_id":"src_micron_hbm_overview"},{"component_id":"hbm-memory:stack","label":"Vertical stack","category":"Capacity in footprint","description":"Eight-high or twelve-high assemblies trade stack height and packaging complexity for more capacity without stretching the package laterally like conventional DIMMs.","economic_unit":"stack height · GB/stack","what_to_watch":"More layers increase capacity but tighten bonding, warpage, thermal, and known-good-die requirements.","metrics":[{"label":"Form","value":"3D-stacked SDRAM"},{"label":"Outcome","value":"capacity + bandwidth"}],"source_id":"src_micron_hbm_overview"},{"component_id":"hbm-memory:interface","label":"Interposer interface","category":"Logic-memory path","description":"The stack sits beside the CPU or GPU on a silicon or redistribution-layer interposer, shortening the path and enabling a very wide parallel connection.","economic_unit":"TB/s per stack · pJ/bit","what_to_watch":"Package routing, signal integrity, and thermals bind memory supply to advanced-packaging capacity.","metrics":[{"label":"HBM3E example","value":">1.2 TB/s per stack"},{"label":"Placement","value":"beside compute"}],"source_id":"src_micron_hbm_overview"}],"example":{"title":"Micron HBM3E: bandwidth comes from width, proximity, and stacking","description":"Micron describes a 1,024-bit interface with 32 independent channels and more than 1.2 TB/s per HBM3E stack. The commercial unit is a qualified stack that must arrive with the package—not a commodity DRAM bit in isolation.","metrics":[{"label":"Interface","value":"1,024-bit"},{"label":"Channels","value":"32"},{"label":"HBM3E","value":">1.2 TB/s"}],"company_ids":["cmp_micron","cmp_sk-hynix","cmp_samsung-electronics"],"source_id":"src_micron_hbm_overview"}},{"layer_id":"advanced-packaging","eyebrow":"07 / The system in a package","title":"Advanced packaging is where compute, memory, power, heat, and yield meet.","description":"A modern AI package can combine logic chiplets and HBM stacks on a silicon or redistribution-layer interposer, then connect that assembly to an organic substrate, power delivery, and a cooling interface. Package area and routing now extend system architecture beyond the reticle.","input":"Known-good logic die · HBM stacks · interposer · substrate · passives","output":"Qualified multi-die accelerator package ready for board assembly","economic_unit":"package · interposer area · bonded die · substrate · package yield","bottlenecks":["Interposer capacity","Advanced substrates","Bonding pitch and yield","Warpage","Power and thermal density"],"components":[{"component_id":"advanced-packaging:logic","label":"Logic die + chiplets","category":"Compute tiles","description":"One or more advanced-node dies provide compute and I/O. Partitioning can improve design reuse and die yield but adds die-to-die interfaces and package dependencies.","economic_unit":"known-good die · chiplet","what_to_watch":"A smaller die can yield better than a monolith, but the package succeeds only if every bonded die and interface works.","metrics":[{"label":"Choice","value":"monolith ↔ chiplets"},{"label":"Gate","value":"known-good die"}],"source_id":"src_tsmc_cowos_platform"},{"component_id":"advanced-packaging:hbm","label":"HBM stacks","category":"Near-memory","description":"Several HBM cubes are placed close to logic so thousands of signal paths can run across the interposer at high bandwidth and lower energy per bit.","economic_unit":"stack · GB · TB/s","what_to_watch":"HBM availability and package slots jointly limit how many complete accelerators can ship.","metrics":[{"label":"Role","value":"capacity + bandwidth"},{"label":"Dependency","value":"memory + package"}],"source_id":"src_tsmc_cowos_platform"},{"component_id":"advanced-packaging:interposer","label":"Interposer + RDL","category":"Dense routing plane","description":"Silicon or redistribution-layer interposers connect logic, HBM, and package bumps with fine-pitch routing beyond what an ordinary substrate can provide.","economic_unit":"mm² · reticle multiple · routing pitch","what_to_watch":"Interposer area, mask stitching, defect exposure, and routing density determine package scale and yield.","metrics":[{"label":"CoWoS-S","value":"up to 3.3× reticle"},{"label":"Example area","value":"about 2,700 mm²"}],"source_id":"src_tsmc_cowos_platform"},{"component_id":"advanced-packaging:substrate","label":"Organic substrate","category":"Board transition","description":"The substrate fans dense package connections out to the circuit board while carrying power, ground, and high-speed signals across materials with different expansion rates.","economic_unit":"substrate · layers · package size","what_to_watch":"Substrate availability, layer count, via density, and coefficient-of-thermal-expansion mismatch affect both capacity and reliability.","metrics":[{"label":"Function","value":"fan-out + power"},{"label":"Boundary","value":"interposer → board"}],"source_id":"src_tsmc_cowos_platform"},{"component_id":"advanced-packaging:thermal","label":"Power + thermal path","category":"System integrity","description":"Bumps, capacitors, lid, thermal interface, and package mechanics must deliver stable power and remove heat without cracking bonds or warping the assembly.","economic_unit":"watts/package · thermal resistance","what_to_watch":"Higher package power raises coupling between electrical design, cooling, materials, and long-term reliability.","metrics":[{"label":"Input","value":"high current"},{"label":"Output","value":"heat to cold plate"}],"source_id":"src_tsmc_cowos_platform"}],"example":{"title":"CoWoS turns a package into a compute platform","description":"TSMC describes CoWoS as a 2.5D platform integrating multiple SoCs and HBM stacks. CoWoS-S supports interposers up to 3.3 times reticle size, showing how package integration expands the system beyond a single-die boundary.","metrics":[{"label":"Interposer","value":"up to 3.3× reticle"},{"label":"Area","value":"about 2,700 mm²"},{"label":"Volume history","value":"since 2012"}],"company_ids":["cmp_tsmc","cmp_ase-technology","cmp_amkor"],"source_id":"src_tsmc_cowos_platform"}},{"layer_id":"assembly-test-inspection","eyebrow":"08 / The qualification gate","title":"Expensive dies create value only after assembly and test prove the complete device.","description":"Wafer probe maps candidate die before dicing. Assembly bonds selected dies into a package. Final test checks electrical behavior across temperature and speed bins; burn-in and system-level test expose failures that appear only under realistic operation. Results feed back into design and process control.","input":"Completed wafer · package materials · test program · product specification","output":"Binned, qualified, traceable devices ready for system integration","economic_unit":"test second · insertion · packaged unit · yield · bin","bottlenecks":["Test time","Probe and socket density","Thermal control","Known-good-die correlation","System-level fault coverage"],"components":[{"component_id":"assembly-test-inspection:wafer-probe","label":"Wafer probe","category":"Pre-package screen","description":"Automated test equipment and probe cards contact die on the wafer, map electrical results, and identify candidates worth packaging.","economic_unit":"die touch · test second · wafer map","what_to_watch":"Probe parallelism and test coverage must catch bad die without damaging pads or consuming excessive cycle time.","metrics":[{"label":"Stage","value":"end of wafer process"},{"label":"Output","value":"die map"}],"source_id":"src_advantest_semiconductor_test"},{"component_id":"assembly-test-inspection:dice-attach","label":"Dice + attach","category":"Physical assembly","description":"The wafer is separated into dies; selected logic, memory, and passive components are placed and bonded into the package flow.","economic_unit":"die placed · bond · package","what_to_watch":"Handling loss, placement accuracy, particles, and bond defects can destroy value already accumulated in expensive known-good dies.","metrics":[{"label":"Input","value":"known-good die"},{"label":"Output","value":"assembled package"}],"source_id":"src_amkor_test_services"},{"component_id":"assembly-test-inspection:final-test","label":"Final test + binning","category":"Electrical qualification","description":"Handlers move packaged devices through testers across temperatures; the test program sorts devices by function, speed, power, and quality grade.","economic_unit":"test second · insertion · bin","what_to_watch":"More coverage improves escape risk but adds test time. Thermal control and interface hardware must match high-power AI devices.","metrics":[{"label":"Stage","value":"after packaging"},{"label":"Output","value":"performance bin"}],"source_id":"src_advantest_semiconductor_test"},{"component_id":"assembly-test-inspection:burn-in","label":"Burn-in + reliability","category":"Early-life screening","description":"Stress conditions accelerate latent failures and validate that package, interconnect, and silicon survive voltage and temperature margins.","economic_unit":"device-hour · stress profile","what_to_watch":"The screen must catch weak units without over-stressing good ones; reliability evidence matters for systems containing many high-value packages.","metrics":[{"label":"Stress","value":"temperature + voltage"},{"label":"Goal","value":"screen latent faults"}],"source_id":"src_advantest_semiconductor_test"},{"component_id":"assembly-test-inspection:system-test","label":"System-level test","category":"Real-use validation","description":"Devices are exercised in a board- or system-like environment to find interaction, firmware, memory, thermal, and high-speed I/O failures missed by isolated component tests.","economic_unit":"system insertion · test minute","what_to_watch":"As packages become systems, fault coverage migrates upward. Watch correlation between component test and actual application failures.","metrics":[{"label":"Environment","value":"application-like"},{"label":"Feedback","value":"test → design + process"}],"source_id":"src_advantest_semiconductor_test"}],"example":{"title":"Test is a loop from wafer to system—not a single pass/fail gate","description":"Advantest places test at design evaluation, wafer test, final test after packaging, and system-level test. Defect analysis feeds back toward design and production, making test data part of yield learning.","metrics":[{"label":"Stage 1","value":"wafer test"},{"label":"Stage 2","value":"final test"},{"label":"Stage 3","value":"system-level test"}],"company_ids":["cmp_advantest","cmp_teradyne","cmp_amkor","cmp_ase-technology"],"source_id":"src_advantest_semiconductor_test"}}],"total":8,"offset":0,"limit":8,"next_offset":null}