The Supply Chain Behind Advanced AI Chips
How a chip becomes a working accelerator: the design tools, materials, manufacturing equipment, fabs, memory, packaging, and testing behind AI compute, and the companies that supply each layer.
- Logic die
- The model’s arithmetic
- Memory stacks
- Weights + activations nearby
- Interposer
- Dense connections
- Package substrate
- Power + connection to the board
What the record shows
- Design is only the beginning. NVIDIA and AMD rely on external foundries, memory suppliers, and packaging processes to turn their designs into physical products.
- Memory and packaging are part of the computing system. HBM stacks sit beside logic dies, and the connections between them determine how quickly data can reach the processor.
- A fab is a chain of specialized processes. Materials, deposition, lithography, etching, and inspection must work together to produce usable dies.
- Capacity must be qualified, not just announced. The manufacturing-project records distinguish planned facilities, construction, and operating capacity.
How the system fits together
An accelerator starts as a description of the calculations it needs to perform. Design software turns that description into a physical layout; materials and manufacturing equipment turn the layout into patterns on a silicon wafer. The wafer is cut into individual chips, or dies, which are combined with memory in a package and tested before installation in a server.
The eight sections below follow that sequence. Each explains what the layer does, shows its parts, and connects it to the companies supplying it. The finished accelerator then enters the racks and clusters described in The Physical Stack Behind AI.
Table of contents
Design the chip
Software tools and chip architecture turn a workload into a manufacturable design.
01EDA & IP
Before a chip can be manufactured, engineers need a precise description of what it should do and where every part should go. Electronic design automation (EDA) software turns that description into a physical layout and checks that it will work. Reusable intellectual property (IP), such as processor cores and interface designs, supplies building blocks that do not have to be designed from scratch. The result is a verified design ready to hand to a manufacturer.
- 01 Logical intent
- Architecture + reusable IP
- 02 Implementation
- Synthesis + place and route
- 03 Verified layout
- Timing, power, signoff
Architecture + RTL
System requirements are partitioned into compute, memory, I/O, control, and security blocks, then expressed as hardware behavior in RTL.
Synopsys ↗Reusable IP
Processor cores, memory controllers, SerDes, PCIe, die-to-die links, and standard-cell libraries let design teams reuse silicon-proven functions instead of rebuilding every interface.
TSMC ↗Logic synthesis
Synthesis converts RTL into a gate-level netlist using foundry libraries while optimizing for timing, power, area, and testability.
Synopsys ↗Place + route
Billions of gates are positioned and their metal connections routed while tools resolve congestion, clocking, power delivery, thermal density, and design rules.
Synopsys ↗Verification + signoff
Simulation, formal checks, timing analysis, power analysis, and layout-versus-schematic checks establish that the implemented design behaves as intended and can be manufactured.
Synopsys ↗From RTL to a manufacturable layout
Synopsys' official EDA overview connects logic synthesis, digital place-and-route, verification, validation, and silicon correlation. The important economic point is the iteration loop: errors caught in software avoid a mask re-spin and lost fab time.
What's inside: 5 components and their sources
System requirements are partitioned into compute, memory, I/O, control, and security blocks, then expressed as hardware behavior in RTL.
What to watch. Watch whether the architecture can meet bandwidth and power targets before implementation complexity hardens.
Processor cores, memory controllers, SerDes, PCIe, die-to-die links, and standard-cell libraries let design teams reuse silicon-proven functions instead of rebuilding every interface.
What to watch. Foundry-node qualification, interface standards, and verification collateral determine whether reusable IP actually shortens the schedule.
Synthesis converts RTL into a gate-level netlist using foundry libraries while optimizing for timing, power, area, and testability.
What to watch. Constraint quality matters: a netlist can be logically correct yet impossible to close physically at the target clock or power envelope.
Billions of gates are positioned and their metal connections routed while tools resolve congestion, clocking, power delivery, thermal density, and design rules.
What to watch. Routing congestion and timing violations often force architectural or floorplan changes late in the cycle, when delay is expensive.
Simulation, formal checks, timing analysis, power analysis, and layout-versus-schematic checks establish that the implemented design behaves as intended and can be manufactured.
What to watch. Coverage gaps and late-found violations create re-spins. First-pass silicon is a schedule and capital event, not only a technical milestone.
Market participants3 companies
Select a company for its roles, financials, relationships, and primary sources. Figures are company-wide USD for the fiscal year shown, not revenue attributable to this layer. Missing values are not reported.
| Company | Role in this layer | Revenue | Capex | PP&E, net |
|---|---|---|---|---|
| ARM · FY2026 | CPU, GPU, interconnect, and system IP licensed to chip designers | $4.9B | $545.0M | $772.0M |
| CDNS · FY2025 | Digital, custom, system, and packaging design software plus reusable IP | $5.3B | $141.9M | $517.0M |
| SNPS · FY2025 | Design, verification, silicon IP, and interface IP used before tape-out | $7.1B | $169.5M | $696.7M |
02Chip & network design
A chip designer decides how the accelerator will divide its work between arithmetic, memory, and communication. More computing units help only if data can reach them quickly enough. The design therefore includes memory controllers and the links that let processors exchange results. This is why the accelerator, the network, and the software that coordinates them need to be designed together. The finished design still depends on a foundry to manufacture it.
- Parallel compute
- Repeated arithmetic blocks
- Interconnect
- Move data between devices
- Memory interfaces
- Keep the processor supplied
Compute engines
Tensor, vector, scalar, and control engines execute the model while cache and scheduling logic try to keep the datapaths occupied.
NVIDIA ↗Memory controllers
HBM controllers and PHYs move weights, activations, and key-value cache between stacked memory and the compute die over a very wide interface.
Micron Technology ↗Scale-up fabric
High-bandwidth links and switch silicon join GPUs within a server or rack so collective operations can treat the domain as a tightly coupled compute unit.
NVIDIA ↗Scale-out fabric
NICs, DPUs, Ethernet or InfiniBand switches, optics, and routing connect accelerator domains to one another and to storage.
NVIDIA ↗Collectives + control
Drivers, communication libraries, topology discovery, and switch control turn physical links into usable all-reduce, broadcast, partitioning, and fault recovery.
NVIDIA ↗GB300 NVL72: one design spans die, link, switch, and rack
NVIDIA documents fifth-generation NVLink at up to 1,800 GB/s per GPU and a 72-GPU rack domain. That is the architectural lesson: accelerator silicon and network silicon are co-designed as one performance envelope.
What's inside: 5 components and their sources
Tensor, vector, scalar, and control engines execute the model while cache and scheduling logic try to keep the datapaths occupied.
What to watch. Compare delivered workload throughput and utilization, not incompatible peak-precision claims.
HBM controllers and PHYs move weights, activations, and key-value cache between stacked memory and the compute die over a very wide interface.
What to watch. Capacity, bandwidth, and energy per bit can each become the binding constraint for a different model or serving regime.
High-bandwidth links and switch silicon join GPUs within a server or rack so collective operations can treat the domain as a tightly coupled compute unit.
What to watch. Topology, oversubscription, latency, and collective efficiency determine how much of link bandwidth becomes model throughput.
NICs, DPUs, Ethernet or InfiniBand switches, optics, and routing connect accelerator domains to one another and to storage.
What to watch. Tail latency, congestion control, optical reach, and failure domains become more important as cluster size grows.
Drivers, communication libraries, topology discovery, and switch control turn physical links into usable all-reduce, broadcast, partitioning, and fault recovery.
What to watch. A fast fabric with poor topology awareness or resiliency strands accelerator time. Watch delivered job completion, not link rate alone.
Market participants6 companies
Select a company for its roles, financials, relationships, and primary sources. Figures are company-wide USD for the fiscal year shown, not revenue attributable to this layer. Missing values are not reported.
| Company | Role in this layer | Revenue | Capex | PP&E, net |
|---|---|---|---|---|
| AMD · FY2025 | EPYC CPUs, Instinct accelerators, adaptive SoCs, and interconnect | $34.6B | $974.0M | $2.3B |
| AVGO · FY2025 | Ethernet switch silicon, optical components, and custom AI accelerators | $63.9B | $623.0M | $2.5B |
| MRVL · FY2026 | Custom compute, electro-optics, switching, and interconnect silicon | $8.2B | $354.1M | $935.0M |
| 2454 | Mobile, edge-AI, networking, and connectivity systems-on-chip | Not reported | Not reported | Not reported |
| NVDA · FY2026 | GPU accelerators, NVLink, networking, and rack-scale systems | $215.9B | Not reported | $10.4B |
| QCOM · FY2025 | Snapdragon compute, radio-frequency, modem, and connectivity platforms | $44.3B | Not reported | $4.7B |
Manufacture the silicon
Materials, equipment, and fabrication turn that design into working dies, one process layer at a time.
03Materials
A chip starts with a flat, polished slice of silicon called a wafer. Making circuits on that surface requires more than silicon: light-sensitive coatings define patterns, gases and chemicals add or remove films, and polishing materials keep the surface level. These materials are used repeatedly as the chip is built. Tiny particles or variations can spoil a circuit, so purity and consistency matter as much as the quantity delivered.
- Process materials
- Gases, resists, precursors
- Polished silicon
- The surface every layer depends on
- Purity is a manufacturing constraint
- Contamination can turn a good design into a failed die
Single-crystal ingot
Electronic-grade polysilicon is melted and a single-crystal ingot is pulled so the wafer begins with a controlled atomic structure and resistivity.
SUMCO ↗Prime silicon wafer
The ingot is sliced, lapped, chemically etched, polished to a mirror finish, cleaned, and inspected before it can enter a leading-edge fab.
SUMCO ↗Resist + mask materials
Photoresist changes chemically under exposure while reticles carry the pattern. Developers, underlayers, pellicles, and cleaning materials support each lithography cycle.
ASML ↗Gases + precursors
Ultra-high-purity precursors create conductive, insulating, and semiconductor films; reactive gases selectively remove material during etch.
Entegris ↗Filtration + handling
Filters, purifiers, wafer carriers, coatings, and cleanroom systems keep particles and trace metals out of materials and process chambers.
Entegris ↗A polished wafer already contains a supply chain
SUMCO shows five controlled wafer-forming stages after crystal growth—slicing, lapping, etching, polishing, then cleaning and inspection. The fab buys a precisely qualified surface, not a generic disc of silicon.
What's inside: 5 components and their sources
Electronic-grade polysilicon is melted and a single-crystal ingot is pulled so the wafer begins with a controlled atomic structure and resistivity.
What to watch. Crystal defects and resistivity variation propagate through every later process; qualification cycles make supplier changes slow.
The ingot is sliced, lapped, chemically etched, polished to a mirror finish, cleaned, and inspected before it can enter a leading-edge fab.
What to watch. Bow, warp, surface particles, and crystal defects affect focus, overlay, and downstream yield.
Photoresist changes chemically under exposure while reticles carry the pattern. Developers, underlayers, pellicles, and cleaning materials support each lithography cycle.
What to watch. Stochastic defects, line-edge roughness, shelf life, and contamination determine whether the printed pattern survives transfer.
Ultra-high-purity precursors create conductive, insulating, and semiconductor films; reactive gases selectively remove material during etch.
What to watch. Purity, delivery stability, chamber compatibility, and residue control affect film uniformity and device reliability.
Filters, purifiers, wafer carriers, coatings, and cleanroom systems keep particles and trace metals out of materials and process chambers.
What to watch. At advanced geometries, contaminants smaller than a visible speck can kill a die; monitor purity at delivery and at point of use.
Market participants10 companies
Select a company for its roles, financials, relationships, and primary sources. Figures are company-wide USD for the fiscal year shown, not revenue attributable to this layer. Missing values are not reported.
| Company | Role in this layer | Revenue | Capex | PP&E, net |
|---|---|---|---|---|
| AI | Carrier, specialty, and advanced-material gases for semiconductor production | Not reported | Not reported | Not reported |
| COHR · FY2026 | Silicon carbide substrates, lasers, and optical components | $7.1B | $1.1B | $3.0B |
| DD · FY2025 | Photoresists, dielectric materials, chemical-mechanical planarization, and packaging materials | $6.8B | Not reported | Not reported |
| ENTG · FY2025 | Specialty materials, gas delivery, filtration, and wafer handling | $3.2B | $299.2M | $1.6B |
| 6488 | Silicon, silicon-on-insulator, and compound-semiconductor wafers | Not reported | Not reported | Not reported |
| LIN · FY2025 | Ultra-high-purity bulk and specialty gases for fabs | $34.0B | $5.3B | $28.3B |
| MRK | Deposition materials, patterning materials, specialty gases, and planarization products | Not reported | Not reported | Not reported |
| 4063 | 300 mm silicon wafers and lithography materials | Not reported | Not reported | Not reported |
| SOI | Silicon-on-insulator and engineered substrates | Not reported | Not reported | Not reported |
| 3436 | Polished, epitaxial, and advanced-node 300 mm silicon wafers | Not reported | Not reported | Not reported |
04Wafer-fab equipment
Manufacturing equipment turns the chip layout into physical structures on a wafer. Deposition tools add thin films. Lithography transfers a pattern into a light-sensitive coating. Etching removes selected material, leaving the desired structure behind. Cleaning, polishing, and measurement keep the process under control. A wafer passes through these operations repeatedly to build the transistors and the wiring that connects them.
- Add a film
- Deposition
- Expose a pattern
- Lithography
- Remove material
- Etch + clean
Deposition
CVD, PVD, and ALD tools deposit conductors, insulators, and semiconductor films with atomic-scale thickness and uniformity control.
ASML ↗Lithography
DUV and EUV scanners project a reticle pattern onto photoresist. Resolution, overlay, focus, source power, and tool availability set the patterning envelope.
ASML ↗Etch + clean
Plasma and wet processes remove exposed material while preserving masked regions; cleans strip residue before the next layer.
ASML ↗Implant + planarize
Ion implantation changes electrical properties; chemical-mechanical polishing flattens the surface so another precisely aligned layer can be built.
ASML ↗Metrology + inspection
Optical and electron-beam systems measure dimensions and overlay, find defects, and classify excursions so recipes or tools can be corrected before more value is added.
KLA ↗One layer is a loop; a chip can repeat it up to 100 times
ASML's manufacturing explainer traces deposition, photoresist, exposure, development, etch, implantation, resist removal, and measurement. Repetition makes uptime, repeatability, and process-control feedback central to fab output.
What's inside: 5 components and their sources
CVD, PVD, and ALD tools deposit conductors, insulators, and semiconductor films with atomic-scale thickness and uniformity control.
What to watch. Uniformity, precursor use, chamber matching, and particle generation determine whether the next patterning step starts from a stable film.
DUV and EUV scanners project a reticle pattern onto photoresist. Resolution, overlay, focus, source power, and tool availability set the patterning envelope.
What to watch. Critical layers depend on scarce, complex systems. Throughput and uptime can matter as much as nominal resolution.
Plasma and wet processes remove exposed material while preserving masked regions; cleans strip residue before the next layer.
What to watch. Profile control, chamber condition, residues, and damage are tightly coupled to yield on dense three-dimensional structures.
Ion implantation changes electrical properties; chemical-mechanical polishing flattens the surface so another precisely aligned layer can be built.
What to watch. Dose uniformity and surface planarity must stay within a shrinking process window across the full wafer.
Optical and electron-beam systems measure dimensions and overlay, find defects, and classify excursions so recipes or tools can be corrected before more value is added.
What to watch. Sensitivity competes with throughput. Sampling plans must find systematic defects without turning process control into the line bottleneck.
Market participants11 companies
Select a company for its roles, financials, relationships, and primary sources. Figures are company-wide USD for the fiscal year shown, not revenue attributable to this layer. Missing values are not reported.
| Company | Role in this layer | Revenue | Capex | PP&E, net |
|---|---|---|---|---|
| 6857 | System-on-chip and memory automated test systems | Not reported | Not reported | Not reported |
| AMAT · FY2025 | Deposition, etch, ion implant, metrology, and packaging equipment | $28.4B | $2.3B | $4.6B |
| ASM | Single-wafer ALD, epitaxy, and vertical furnace systems | Not reported | Not reported | Not reported |
| ASML / ASML · FY2025 | EUV, High-NA EUV, DUV lithography, metrology, and computational lithography | Not reported | Not reported | Not reported |
| BESI | Die attach, hybrid bonding, molding, plating, and trim/form systems | Not reported | Not reported | Not reported |
| 6146 | Grinding, polishing, laser saw, and dicing systems | Not reported | Not reported | Not reported |
| KLAC · FY2026 | Inspection, metrology, computational analytics, and process-control systems | $13.6B | $375.9M | $1.4B |
| LRCX · FY2026 | Plasma etch, deposition, wafer clean, and advanced packaging equipment | $23.2B | Not reported | $2.9B |
| 7735 | Single-wafer cleaning, batch cleaning, coater/developer, and annealing systems | Not reported | Not reported | Not reported |
| TER · FY2025 | System-on-chip, memory, storage, and wireless test platforms | $3.2B | $224.0M | $563.0M |
| 8035 | Coater/developer, thermal processing, etch, deposition, and wafer cleaning | Not reported | Not reported | Not reported |
05Foundries & IDMs
A foundry operates the factories that manufacture chips for other companies. An integrated device manufacturer (IDM) also designs its own chips. Both must turn a working process into repeatable production: the same design appears many times across a wafer, but not every copy will work. The share of usable chips is called yield. Factory capacity becomes useful supply only when the process produces enough good chips and customers have qualified them.
- One wafer, many copies
- Each rectangle represents a die
- Usable die
- Yield determines output
Tape-out + masks
The signed-off layout is fractured into mask data and checked against foundry rules before production reticles are released.
TSMC ↗Wafer starts
A wafer lot is introduced to the line and routed through the qualified process flow, repeatedly visiting tool groups over months.
ASML ↗Process integration
Transistor, interconnect, patterning, materials, and thermal steps must work as one reproducible process rather than as isolated tool recipes.
TSMC ↗Yield learning
Inspection, electrical test, failure analysis, and statistical process control identify defect mechanisms and raise the share of dies that meet specification.
KLA ↗Qualification + ramp
Process reliability, package interaction, product test, and customer signoff convert engineering lots into repeatable high-volume shipments.
National Institute of Standards and Technology ↗TSMC Arizona Fab 1: operation is a state, not an announcement
The NIST project record distinguishes construction, production milestones, technology scope, and program commitments. Semiconductor capacity becomes economically relevant only after tools, process, yield, and customer qualification converge.
What's inside: 5 components and their sources
The signed-off layout is fractured into mask data and checked against foundry rules before production reticles are released.
What to watch. Mask cost and queue time make late design changes expensive; first-pass success protects both schedule and wafer capacity.
A wafer lot is introduced to the line and routed through the qualified process flow, repeatedly visiting tool groups over months.
What to watch. Announced shell capacity is not the same as installed, qualified, and customer-allocated wafer starts.
Transistor, interconnect, patterning, materials, and thermal steps must work as one reproducible process rather than as isolated tool recipes.
What to watch. A nominal node label does not reveal performance, density, yield, or customer readiness; watch qualified products and volume state.
Inspection, electrical test, failure analysis, and statistical process control identify defect mechanisms and raise the share of dies that meet specification.
What to watch. Yield on a large accelerator die can dominate delivered cost and volume. Early ramps should not be treated like mature output.
Process reliability, package interaction, product test, and customer signoff convert engineering lots into repeatable high-volume shipments.
What to watch. Expected operation dates, risk production, qualification, and volume production are different milestones and should remain distinct.
Market participants15 companies
Select a company for its roles, financials, relationships, and primary sources. Figures are company-wide USD for the fiscal year shown, not revenue attributable to this layer. Missing values are not reported.
| Company | Role in this layer | Revenue | Capex | PP&E, net |
|---|---|---|---|---|
| GFS · FY2025 | Radio-frequency, silicon photonics, power, embedded memory, and mature-node logic | Not reported | Not reported | Not reported |
| 688347 / 1347 | Embedded non-volatile memory, power, analog, and mature-node logic | Not reported | Not reported | Not reported |
| IFX | Silicon carbide, gallium nitride, power, automotive, and microcontroller products | Not reported | Not reported | Not reported |
| INTC · FY2025 | CPUs, accelerators, Intel 18A process, and foundry services | $52.9B | $14.6B | Not reported |
| MCHP · FY2026 | Microcontrollers, field-programmable gate arrays, analog, timing, and connectivity | $4.7B | $91.1M | $1.1B |
| NXPI · FY2025 | Automotive processors, microcontrollers, radio-frequency, and secure connectivity | $12.3B | $397.0M | $3.0B |
| ON · FY2025 | Silicon carbide, power management, and intelligent sensing | $6.0B | $341.2M | $3.4B |
| 6723 | Microcontrollers, system-on-chip, analog, and power products | Not reported | Not reported | Not reported |
| 005930 | Leading-edge logic, foundry services, image sensors, and memory | Not reported | Not reported | Not reported |
| 688981 / 0981 | Logic and specialty wafer manufacturing across multiple process generations | Not reported | Not reported | Not reported |
| STM / STMPA · FY2025 | Silicon carbide, microcontrollers, sensors, analog, and automotive semiconductors | $11.8B | Not reported | $11.1B |
| TXN · FY2025 | Analog, power-management, and embedded-processing semiconductors | $17.7B | $4.6B | $12.3B |
| TSEM / TSEM · FY2025 | Radio-frequency, power, image-sensor, silicon-photonics, and analog processes | $1.6B | $444.4M | $1.5B |
| 2330 / TSM · FY2024 | N2, A16, N3, N4/N5, specialty processes, and wafer manufacturing | Not reported | Not reported | Not reported |
| 2303 / UMC · FY2024 | Logic and specialty technologies across 300 mm and 200 mm fabs | Not reported | Not reported | Not reported |
Assemble the package
Memory, advanced packaging, and testing turn individual dies into a qualified computing component.
06HBM & memory
An AI processor needs a steady supply of model weights and other data. High-bandwidth memory (HBM) puts several memory dies in a vertical stack beside the processor, with many parallel connections carrying data between them. Connections pass through the silicon itself using through-silicon vias, or TSVs. Stacking brings memory close to compute, but every die and connection must work, and heat must still escape from the finished package.
- Memory dies
- Stack capacity vertically
- Vertical connections
- Through-silicon vias + microbumps
- Base + package interface
- Move data into the processor
DRAM dies
Multiple DRAM dies supply the capacity and parallel channels. Each layer must be tested because one weak die can compromise the stack.
Micron Technology ↗TSVs + microbumps
Thousands of vertical vias and fine-pitch bonds carry data, power, and control through the stack over much shorter paths than a conventional module.
Micron Technology ↗Base die + channels
An optional base die and channel architecture organize the ultra-wide interface and connect the stack to package routing.
Micron Technology ↗Vertical stack
Eight-high or twelve-high assemblies trade stack height and packaging complexity for more capacity without stretching the package laterally like conventional DIMMs.
Micron Technology ↗Interposer interface
The stack sits beside the CPU or GPU on a silicon or redistribution-layer interposer, shortening the path and enabling a very wide parallel connection.
Micron Technology ↗Micron HBM3E: bandwidth comes from width, proximity, and stacking
Micron describes a 1,024-bit interface with 32 independent channels and more than 1.2 TB/s per HBM3E stack. The commercial unit is a qualified stack that must arrive with the package—not a commodity DRAM bit in isolation.
What's inside: 5 components and their sources
Multiple DRAM dies supply the capacity and parallel channels. Each layer must be tested because one weak die can compromise the stack.
What to watch. Bit density, process yield, speed grade, and power all affect how many stackable dies emerge from a wafer.
Thousands of vertical vias and fine-pitch bonds carry data, power, and control through the stack over much shorter paths than a conventional module.
What to watch. Via defects, bond alignment, and thermal stress compound across stacked dies.
An optional base die and channel architecture organize the ultra-wide interface and connect the stack to package routing.
What to watch. Controller compatibility and channel utilization determine whether headline bandwidth is reachable by the workload.
Eight-high or twelve-high assemblies trade stack height and packaging complexity for more capacity without stretching the package laterally like conventional DIMMs.
What to watch. More layers increase capacity but tighten bonding, warpage, thermal, and known-good-die requirements.
The stack sits beside the CPU or GPU on a silicon or redistribution-layer interposer, shortening the path and enabling a very wide parallel connection.
What to watch. Package routing, signal integrity, and thermals bind memory supply to advanced-packaging capacity.
Market participants4 companies
Select a company for its roles, financials, relationships, and primary sources. Figures are company-wide USD for the fiscal year shown, not revenue attributable to this layer. Missing values are not reported.
| Company | Role in this layer | Revenue | Capex | PP&E, net |
|---|---|---|---|---|
| 285A | NAND flash and solid-state storage; not a current HBM supplier | Not reported | Not reported | Not reported |
| MU · FY2025 | HBM, DDR, NAND, managed storage, and advanced memory packaging | $37.4B | $15.9B | Not reported |
| 005930 | HBM, DDR, NAND, and enterprise storage | Not reported | Not reported | Not reported |
| 000660 | HBM, DDR, NAND, and enterprise storage | Not reported | Not reported | Not reported |
07Advanced packaging
Packaging connects the processor and memory into a component that can be installed on a circuit board. In an advanced AI package, logic dies and HBM stacks sit on a dense wiring layer called an interposer. Beneath it, a substrate connects the assembly to the board and supplies power. Packaging is therefore part of the system design: its wiring, size, power delivery, and cooling interface affect what the chips can do together.
- Logic die
- The model’s arithmetic
- Memory stacks
- Weights + activations nearby
- Interposer
- Dense connections
- Package substrate
- Power + connection to the board
Logic die + chiplets
One or more advanced-node dies provide compute and I/O. Partitioning can improve design reuse and die yield but adds die-to-die interfaces and package dependencies.
TSMC ↗HBM stacks
Several HBM cubes are placed close to logic so thousands of signal paths can run across the interposer at high bandwidth and lower energy per bit.
TSMC ↗Interposer + RDL
Silicon or redistribution-layer interposers connect logic, HBM, and package bumps with fine-pitch routing beyond what an ordinary substrate can provide.
TSMC ↗Organic substrate
The substrate fans dense package connections out to the circuit board while carrying power, ground, and high-speed signals across materials with different expansion rates.
TSMC ↗Power + thermal path
Bumps, capacitors, lid, thermal interface, and package mechanics must deliver stable power and remove heat without cracking bonds or warping the assembly.
TSMC ↗CoWoS turns a package into a compute platform
TSMC describes CoWoS as a 2.5D platform integrating multiple SoCs and HBM stacks. CoWoS-S supports interposers up to 3.3 times reticle size, showing how package integration expands the system beyond a single-die boundary.
What's inside: 5 components and their sources
One or more advanced-node dies provide compute and I/O. Partitioning can improve design reuse and die yield but adds die-to-die interfaces and package dependencies.
What to watch. A smaller die can yield better than a monolith, but the package succeeds only if every bonded die and interface works.
Several HBM cubes are placed close to logic so thousands of signal paths can run across the interposer at high bandwidth and lower energy per bit.
What to watch. HBM availability and package slots jointly limit how many complete accelerators can ship.
Silicon or redistribution-layer interposers connect logic, HBM, and package bumps with fine-pitch routing beyond what an ordinary substrate can provide.
What to watch. Interposer area, mask stitching, defect exposure, and routing density determine package scale and yield.
The substrate fans dense package connections out to the circuit board while carrying power, ground, and high-speed signals across materials with different expansion rates.
What to watch. Substrate availability, layer count, via density, and coefficient-of-thermal-expansion mismatch affect both capacity and reliability.
Bumps, capacitors, lid, thermal interface, and package mechanics must deliver stable power and remove heat without cracking bonds or warping the assembly.
What to watch. Higher package power raises coupling between electrical design, cooling, materials, and long-term reliability.
Market participants10 companies
Select a company for its roles, financials, relationships, and primary sources. Figures are company-wide USD for the fiscal year shown, not revenue attributable to this layer. Missing values are not reported.
| Company | Role in this layer | Revenue | Capex | PP&E, net |
|---|---|---|---|---|
| AMKR · FY2025 | Flip-chip, wafer-level, system-in-package, and 2.5D packaging | $6.7B | $904.6M | Not reported |
| 3711 / ASX · FY2025 | 2.5D/3D integration, fan-out, flip-chip, and system-in-package | Not reported | Not reported | Not reported |
| 4062 | Build-up substrates for high-performance processors and advanced packages | Not reported | Not reported | Not reported |
| INTC · FY2025 | EMIB, Foveros, and glass-substrate development | $52.9B | $14.6B | Not reported |
| 600584 | Wafer-level, flip-chip, system-in-package, and heterogeneous integration | Not reported | Not reported | Not reported |
| 8046 | Flip-chip ball-grid-array substrates and high-density printed circuit boards | Not reported | Not reported | Not reported |
| 005930 | 2.5D/3D integration and foundry packaging | Not reported | Not reported | Not reported |
| 000660 | Through-silicon-via HBM assembly and next-generation memory packaging | Not reported | Not reported | Not reported |
| 2330 / TSM · FY2024 | CoWoS, InFO, and system-on-integrated-chip packaging | Not reported | Not reported | Not reported |
| 3037 | Flip-chip substrates, high-density interconnect boards, and carrier boards | Not reported | Not reported | Not reported |
08Assembly, test & inspection
Testing starts while the chips are still on the wafer. Probe equipment checks individual dies so manufacturers can avoid putting defective parts into an expensive package. After assembly, further tests check electrical behavior, speed, temperature tolerance, and reliability. Some failures appear only when the device runs as part of a system. The output of this layer is a qualified component, with results that can also guide changes to the design and manufacturing process.
- Probe the wafer
- Identify usable dies
- Test the package
- Electrical + thermal checks
- Qualify the output
- Ready for the system
Wafer probe
Automated test equipment and probe cards contact die on the wafer, map electrical results, and identify candidates worth packaging.
Advantest ↗Dice + attach
The wafer is separated into dies; selected logic, memory, and passive components are placed and bonded into the package flow.
Amkor Technology ↗Final test + binning
Handlers move packaged devices through testers across temperatures; the test program sorts devices by function, speed, power, and quality grade.
Advantest ↗Burn-in + reliability
Stress conditions accelerate latent failures and validate that package, interconnect, and silicon survive voltage and temperature margins.
Advantest ↗System-level test
Devices are exercised in a board- or system-like environment to find interaction, firmware, memory, thermal, and high-speed I/O failures missed by isolated component tests.
Advantest ↗Test is a loop from wafer to system—not a single pass/fail gate
Advantest places test at design evaluation, wafer test, final test after packaging, and system-level test. Defect analysis feeds back toward design and production, making test data part of yield learning.
What's inside: 5 components and their sources
Automated test equipment and probe cards contact die on the wafer, map electrical results, and identify candidates worth packaging.
What to watch. Probe parallelism and test coverage must catch bad die without damaging pads or consuming excessive cycle time.
The wafer is separated into dies; selected logic, memory, and passive components are placed and bonded into the package flow.
What to watch. Handling loss, placement accuracy, particles, and bond defects can destroy value already accumulated in expensive known-good dies.
Handlers move packaged devices through testers across temperatures; the test program sorts devices by function, speed, power, and quality grade.
What to watch. More coverage improves escape risk but adds test time. Thermal control and interface hardware must match high-power AI devices.
Stress conditions accelerate latent failures and validate that package, interconnect, and silicon survive voltage and temperature margins.
What to watch. The screen must catch weak units without over-stressing good ones; reliability evidence matters for systems containing many high-value packages.
Devices are exercised in a board- or system-like environment to find interaction, firmware, memory, thermal, and high-speed I/O failures missed by isolated component tests.
What to watch. As packages become systems, fault coverage migrates upward. Watch correlation between component test and actual application failures.
Market participants8 companies
Select a company for its roles, financials, relationships, and primary sources. Figures are company-wide USD for the fiscal year shown, not revenue attributable to this layer. Missing values are not reported.
| Company | Role in this layer | Revenue | Capex | PP&E, net |
|---|---|---|---|---|
| 6857 | High-speed test platforms for AI accelerators and HBM | Not reported | Not reported | Not reported |
| AMKR · FY2025 | Assembly, wafer probe, final test, and system-level test | $6.7B | $904.6M | Not reported |
| 3711 / ASX · FY2025 | Wafer probe, final test, assembly, and system-level test | Not reported | Not reported | Not reported |
| BESI | Hybrid bonding and die placement equipment | Not reported | Not reported | Not reported |
| 6146 | Wafer singulation and thinning for advanced packages | Not reported | Not reported | Not reported |
| 600584 | Package assembly and semiconductor test services | Not reported | Not reported | Not reported |
| KLAC · FY2026 | Package, substrate, wafer, and reticle inspection | $13.6B | $375.9M | $1.4B |
| TER · FY2025 | Wafer sort and packaged-device test systems | $3.2B | $224.0M | $563.0M |
Research intensity versus capital intensity
Latest fiscal year where revenue, R&D, and capital expenditures coexist. Bubble area follows company-wide revenue; ratios are derived from reported SEC XBRL facts.
17 companies meet the strict same-year comparability rule. Click a bubble for the underlying fiscal year and filing source.
Nine tracked U.S. projects, with status kept explicit
City-level orientation only. A program can represent several announced facilities; cost is shown only when the cited source reports a comparable program value.
| Project | Status | Scope & announced products | Reported cost | Primary source |
|---|---|---|---|---|
Peoria, Arizona | under-construction | advanced packaging and test campus advanced packaging · semiconductor test | $7.00B | Amkor Technology ↗ |
Chandler, Arizona | under-construction | two leading-edge logic fabs leading-edge logic · foundry capacity | Not reported | National Institute of Standards and Technology ↗ |
Boise, Idaho | under-construction | leading-edge memory fabs and R&D DRAM · advanced memory | Not reported | Micron Technology ↗ |
Clay, New York | planned | memory manufacturing campus leading-edge DRAM | $100.00B | National Institute of Standards and Technology ↗ |
West Lafayette, Indiana | planned | advanced packaging and R&D campus HBM advanced packaging | $3.87B | SK hynix ↗ |
Sherman, Texas | under-construction | analog and embedded semiconductor fab campus analog semiconductors · embedded processors | Not reported | National Institute of Standards and Technology ↗ |
Phoenix, Arizona | operational | leading-edge logic fab N4 logic wafers | Not reported | National Institute of Standards and Technology ↗ |
Phoenix, Arizona | under-construction | leading-edge logic fab N3 logic wafers | Not reported | National Institute of Standards and Technology ↗ |
Phoenix, Arizona | announced | three fabs, two advanced-packaging facilities, and R&D center advanced logic · advanced packaging | $100.00B | TSMC ↗ |
Company-wide capex since 2017
Annual sum across covered issuers with a reported USD Company Facts value. The coverage set changes by year; this is not total industry capex.
Missing is not zero. Each bar sums only the 5–20 covered companies reporting in that year.
Methodology and data access
One snapshot, two interfaces
The page, versioned HTTP API, and read-only MCP tools resolve against the same bundled snapshot. IDs are stable strings; pagination is deterministic; no interface recomputes facts from a second store.
- /api/semiconductors — coverage and dimensions
- /api/semiconductors/snapshot — full immutable V1 capture
- /api/semiconductors/explainers — eight sourced interactive layers
- /api/semiconductors/companies · projects · financials
- /api/semiconductors/relationships · sources · trade
- MCP:
search_semiconductor_intelligence·get_semiconductor_company·list_semiconductor_sources
Universe
54 current public companies selected for direct relevance across eight physical layers. Multiple membership is retained.
Financials
2017 onward, extracted from SEC Company Facts. Original unit, period, filing date, tag, source, and reported status are preserved.
Trade
V1 publishes a revision-labeled HTS heading codebook but no trade values. Headings 3818, 8486, 8541, and 8542 include products beyond advanced AI chips; an honest chart needs subheading concordance first.
Citation
MTS Intelligence, “The Supply Chain Behind Advanced AI Chips,” 2026-08-26, snapshot semiconductors-v1-9ec9a9512e4ae1d5.
Primary sources
Primary evidence used in V1
- Our Technology In-Depth: Semiconductor Test ↗
Advantest · official-company - AMD fiscal 2025 Form 10-K ↗
U.S. Securities and Exchange Commission · regulatory - Amkor Technology Breaks Ground on New Semiconductor Advanced Packaging and Test Facility ↗
Amkor Technology · official-company - IC Semiconductor Test Services ↗
Amkor Technology · official-company - How Microchips Are Made ↗
ASML · official-company - Intel and ASML strengthen their collaboration to drive High-NA into manufacturing in 2025 ↗
ASML · official-company - Lithography Principles ↗
ASML · official-company - Broadcom fiscal 2024 annual report ↗
U.S. Securities and Exchange Commission · regulatory - Deposition Materials and Contamination Control ↗
Entegris · official-company - Chip Manufacturing 101: Process Control ↗
KLA · official-company - High-Bandwidth Memory (HBM) ↗
Micron Technology · official-company - Micron U.S. expansion ↗
Micron Technology · official-company - CHIPS for America Awards ↗
National Institute of Standards and Technology · government - Micron Technology Memory Chip Manufacturing Investment ↗
National Institute of Standards and Technology · government - Micron New York Semiconductor Manufacturing ↗
National Institute of Standards and Technology · government - TSMC Arizona Corporation ↗
National Institute of Standards and Technology · government - NVIDIA fiscal 2025 annual report ↗
U.S. Securities and Exchange Commission · regulatory - NVIDIA NVL72 AI Factory: System Hardware and Components ↗
NVIDIA · official-company - Qualcomm fiscal 2025 annual report ↗
U.S. Securities and Exchange Commission · regulatory - ADVANCED MICRO DEVICES INC SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - AMKOR TECHNOLOGY, INC. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - APPLIED MATERIALS INC /DE SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - ARM HOLDINGS PLC /UK SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - ASE Technology Holding Co., Ltd. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - ASML HOLDING NV SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - Broadcom Inc. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - CADENCE DESIGN SYSTEMS, INC. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - COHERENT CORP. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - DUPONT DE NEMOURS, INC. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - Entegris, Inc. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - GLOBALFOUNDRIES Inc. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - INTEL CORP SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - KLA CORP SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - LAM RESEARCH CORPORATION SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - Linde plc SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - Marvell Technology, Inc. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - MICROCHIP TECHNOLOGY INCORPORATED SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - Micron Technology, Inc. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - NVIDIA CORP SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - NXP Semiconductors N.V. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - ON SEMICONDUCTOR CORPORATION SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - QUALCOMM INC/DE SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - STMicroelectronics N.V. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - SYNOPSYS INC SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - TERADYNE, INC. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - TEXAS INSTRUMENTS INCORPORATED SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - TOWER SEMICONDUCTOR LTD. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - Taiwan Semiconductor Manufacturing Company Limited SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - United Microelectronics Corporation SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory - SK hynix Signs Investment Agreement for Advanced Chip Packaging with Indiana ↗
SK hynix · official-company - Silicon Wafer Production Processes ↗
SUMCO · official-company - What is Electronic Design Automation (EDA)? ↗
Synopsys · official-company - CoWoS Advanced Packaging Platform ↗
TSMC · official-company - Dedicated Foundry Services ↗
TSMC · official-company - High-Performance Computing Platform ↗
TSMC · official-company - TSMC Intends to Expand Its Investment in the United States to US$165 Billion ↗
TSMC · official-company - Harmonized Tariff Schedule of the United States ↗
U.S. International Trade Commission · official-standard