The Supply Chain Behind Advanced AI Chips

Figure 1 · Interactive system decoder

Follow the accelerator from blueprint to qualified package

The layer selector is the control. Each choice replaces the thesis, system map, five-part process, bottlenecks, worked example, evidence, and market participants. Select a node inside any visual to inspect it.

01 / 08EDA & IP40 clickable components

01 / The executable blueprint

A chip is debugged in software before it becomes geometry.

Architecture becomes register-transfer logic, reusable IP, a gate-level netlist, placed-and-routed geometry, and finally a verified tape-out package. Each handoff constrains power, performance, area, schedule, and manufacturability before a foundry touches a wafer.

Input: Workload requirements · architecture · foundry design rules
Output: Verified layout database · masks-ready tape-out · embedded IP licenses

Economic unitEDA subscription · IP license/royalty · engineering seat · tape-out

Where the layer binds

Verification closureTiming and power closureFoundry-qualified IPEngineering scheduleMask re-spin risk

Clickable system map5 components · choose one

Logical intent / component intelligence

Architecture + RTL

System requirements are partitioned into compute, memory, I/O, control, and security blocks, then expressed as hardware behavior in RTL.

Watch: Watch whether the architecture can meet bandwidth and power targets before implementation complexity hardens.

Synopsys ↗

Economic unitengineer-month · design block

Inputworkload + constraints

OutputRTL + block plan

Attributable worked example

From RTL to a manufacturable layout

Synopsys' official EDA overview connects logic synthesis, digital place-and-route, verification, validation, and silicon correlation. The important economic point is the iteration loop: errors caught in software avoid a mask re-spin and lost fab time.

FlowRTL → gates → layout

Closuretiming · power · function

Release gatesignoff

What is Electronic Design Automation (EDA)? · Synopsys ↗

02 / The system architecture

The accelerator is only useful when compute, memory, and fabric stay in balance.

Chip and network designers decide the math engines, on-package memory interfaces, host links, scale-up domain, scale-out fabric, and software-visible topology. Useful AI throughput depends on feeding the arithmetic units and coordinating many devices, not peak FLOPS alone.

Input: Model behavior · latency target · power envelope · available process and packaging
Output: Accelerator, switch, NIC, DPU, and fabric designs ready for tape-out

Economic unitchip · board · port · bandwidth · rack-scale system

Where the layer binds

Memory bandwidthAll-to-all communicationSerDes reach and powerSoftware collectivesPackage and reticle limits

Clickable system map5 components · choose one

Accelerator die / component intelligence

Compute engines

Tensor, vector, scalar, and control engines execute the model while cache and scheduling logic try to keep the datapaths occupied.

Watch: Compare delivered workload throughput and utilization, not incompatible peak-precision claims.

NVIDIA ↗

Economic unitaccelerator · FLOPS · tokens/s

Unitaccelerator

Outcomeuseful throughput

Attributable worked example

GB300 NVL72: one design spans die, link, switch, and rack

NVIDIA documents fifth-generation NVLink at up to 1,800 GB/s per GPU and a 72-GPU rack domain. That is the architectural lesson: accelerator silicon and network silicon are co-designed as one performance envelope.

GPUs72

Per-GPU link1,800 GB/s

Switch trays9

NVIDIA NVL72 AI Factory: System Hardware and Components · NVIDIA ↗

03 / The purity stack

Every patterned layer begins with materials clean enough not to become defects.

A polished silicon wafer is only the substrate. Photoresists, masks, deposition precursors, process gases, wet chemicals, slurries, filtration, and wafer handling enter repeatedly as the device is built layer by layer. Consistency and contamination control are yield inputs.

Input: Electronic-grade polysilicon · gases · chemicals · metals · polymers
Output: Prime wafers and process materials delivered to exact purity and geometry specifications

Economic unitwafer · liter · kilogram · cylinder · defect density

Where the layer binds

PurityParticle and metal contaminationWafer flatnessPrecursor consistencySingle-source qualification

Clickable system map5 components · choose one

Silicon foundation / component intelligence

Single-crystal ingot

Electronic-grade polysilicon is melted and a single-crystal ingot is pulled so the wafer begins with a controlled atomic structure and resistivity.

Watch: Crystal defects and resistivity variation propagate through every later process; qualification cycles make supplier changes slow.

SUMCO ↗

Economic unitkilogram · ingot · crystal yield

MethodCZ crystal growth

Outputmonocrystalline ingot

Attributable worked example

A polished wafer already contains a supply chain

SUMCO shows five controlled wafer-forming stages after crystal growth—slicing, lapping, etching, polishing, then cleaning and inspection. The fab buys a precisely qualified surface, not a generic disc of silicon.

Wafer forming5 stages

Starting sliceabout 1 mm

Releaseclean + inspect

Silicon Wafer Production Processes · SUMCO ↗

04 / The process loop

A fab repeats deposition, patterning, etch, and measurement until a device emerges.

Leading-edge manufacturing is not one machine. Tool families add films, print patterns, remove material, alter electrical properties, clean surfaces, and measure the result. Data from inspection and metrology feeds the next adjustment, while uptime and throughput govern factory economics.

Input: Prime wafer · reticle · process recipe · gases and chemicals
Output: Patterned wafer with stacked transistor and interconnect layers

Economic unittool · wafer pass · wafers/hour · uptime · installed base service

Where the layer binds

EUV availabilityProcess uniformityChamber uptimeOverlay and critical dimensionsDefect detection sensitivity

Clickable system map5 components · choose one

Add material / component intelligence

Deposition

CVD, PVD, and ALD tools deposit conductors, insulators, and semiconductor films with atomic-scale thickness and uniformity control.

Watch: Uniformity, precursor use, chamber matching, and particle generation determine whether the next patterning step starts from a stable film.

ASML ↗

Economic unitwafer pass · film thickness · wafers/hour

Actionadd a thin film

Controlthickness + uniformity

Attributable worked example

One layer is a loop; a chip can repeat it up to 100 times

ASML's manufacturing explainer traces deposition, photoresist, exposure, development, etch, implantation, resist removal, and measurement. Repetition makes uptime, repeatability, and process-control feedback central to fab output.

Front-end flowhundreds of steps

Layer loopup to 100 repeats

Feedbackmetrology → equipment

How Microchips Are Made · ASML ↗

05 / The yield factory

The foundry converts a design file into repeatable, qualified good die.

After tape-out, masks and process recipes send wafer lots through hundreds of front-end steps. A foundry or IDM manages cycle time, equipment availability, process control, yield learning, customer qualification, and volume ramp across a technology platform.

Input: Signed-off layout · mask set · process design kit · wafer starts
Output: Tested wafer · known-good logic die · qualified production capacity

Economic unitwafer start · wafer/month · good die · yield · process node

Where the layer binds

Yield rampCycle timeQualified wafer capacityMask and process readinessCustomer concentration and allocation

Clickable system map5 components · choose one

Customer handoff / component intelligence

Tape-out + masks

The signed-off layout is fractured into mask data and checked against foundry rules before production reticles are released.

Watch: Mask cost and queue time make late design changes expensive; first-pass success protects both schedule and wafer capacity.

TSMC ↗

Economic unitmask set · tape-out · NRE

Inputverified layout

Releasemask set

Attributable worked example

TSMC Arizona Fab 1: operation is a state, not an announcement

The NIST project record distinguishes construction, production milestones, technology scope, and program commitments. Semiconductor capacity becomes economically relevant only after tools, process, yield, and customer qualification converge.

TechnologyN4

Wafer300 mm

Stateoperational

TSMC Arizona Corporation · National Institute of Standards and Technology ↗

06 / The bandwidth wall

HBM moves memory beside compute and widens the road between them.

High-bandwidth memory stacks DRAM dies vertically, connects them with through-silicon vias and microbumps, and places the stack beside logic on an interposer. Capacity, bandwidth, thermals, stack yield, and packaging availability now shape accelerator output.

Input: DRAM wafer · base die · TSV process · known-good dies
Output: Qualified HBM stack integrated beside an accelerator

Economic unitstack · gigabyte · TB/s · energy/bit · known-good die

Where the layer binds

DRAM die yieldTSV and microbump yieldStack heightThermal envelopePackaging co-capacity

Clickable system map5 components · choose one

Memory cells / component intelligence

DRAM dies

Multiple DRAM dies supply the capacity and parallel channels. Each layer must be tested because one weak die can compromise the stack.

Watch: Bit density, process yield, speed grade, and power all affect how many stackable dies emerge from a wafer.

Micron Technology ↗

Economic unitgigabit die · known-good die

Rolestore model state

Gateknown-good die

Attributable worked example

Micron HBM3E: bandwidth comes from width, proximity, and stacking

Micron describes a 1,024-bit interface with 32 independent channels and more than 1.2 TB/s per HBM3E stack. The commercial unit is a qualified stack that must arrive with the package—not a commodity DRAM bit in isolation.

Interface1,024-bit

Channels32

HBM3E>1.2 TB/s

High-Bandwidth Memory (HBM) · Micron Technology ↗

07 / The system in a package

Advanced packaging is where compute, memory, power, heat, and yield meet.

A modern AI package can combine logic chiplets and HBM stacks on a silicon or redistribution-layer interposer, then connect that assembly to an organic substrate, power delivery, and a cooling interface. Package area and routing now extend system architecture beyond the reticle.

Input: Known-good logic die · HBM stacks · interposer · substrate · passives
Output: Qualified multi-die accelerator package ready for board assembly

Economic unitpackage · interposer area · bonded die · substrate · package yield

Where the layer binds

Interposer capacityAdvanced substratesBonding pitch and yieldWarpagePower and thermal density

Clickable system map5 components · choose one

Compute tiles / component intelligence

Logic die + chiplets

One or more advanced-node dies provide compute and I/O. Partitioning can improve design reuse and die yield but adds die-to-die interfaces and package dependencies.

Watch: A smaller die can yield better than a monolith, but the package succeeds only if every bonded die and interface works.

TSMC ↗

Economic unitknown-good die · chiplet

Choicemonolith ↔ chiplets

Gateknown-good die

Attributable worked example

CoWoS turns a package into a compute platform

TSMC describes CoWoS as a 2.5D platform integrating multiple SoCs and HBM stacks. CoWoS-S supports interposers up to 3.3 times reticle size, showing how package integration expands the system beyond a single-die boundary.

Interposerup to 3.3× reticle

Areaabout 2,700 mm²

Volume historysince 2012

CoWoS Advanced Packaging Platform · TSMC ↗

08 / The qualification gate

Expensive dies create value only after assembly and test prove the complete device.

Wafer probe maps candidate die before dicing. Assembly bonds selected dies into a package. Final test checks electrical behavior across temperature and speed bins; burn-in and system-level test expose failures that appear only under realistic operation. Results feed back into design and process control.

Input: Completed wafer · package materials · test program · product specification
Output: Binned, qualified, traceable devices ready for system integration

Economic unittest second · insertion · packaged unit · yield · bin

Where the layer binds

Test timeProbe and socket densityThermal controlKnown-good-die correlationSystem-level fault coverage

Clickable system map5 components · choose one

Pre-package screen / component intelligence

Wafer probe

Automated test equipment and probe cards contact die on the wafer, map electrical results, and identify candidates worth packaging.

Watch: Probe parallelism and test coverage must catch bad die without damaging pads or consuming excessive cycle time.

Advantest ↗

Economic unitdie touch · test second · wafer map

Stageend of wafer process

Outputdie map

Attributable worked example

Test is a loop from wafer to system—not a single pass/fail gate

Advantest places test at design evaluation, wafer test, final test after packaging, and system-level test. Defect analysis feeds back toward design and production, making test data part of yield learning.

Stage 1wafer test

Stage 2final test

Stage 3system-level test

Our Technology In-Depth: Semiconductor Test · Advantest ↗

How to read: layer changes replace the full explanatory workspace; diagram nodes and component cards are synchronized. Company buttons open the same sourced dossiers used elsewhere in the publication. Open the machine-readable explainers ↗

Figure 2 · Financial intensity

Research intensity versus capital intensity

Latest fiscal year where revenue, R&D, and capital expenditures coexist. Bubble area follows company-wide revenue; ratios are derived from reported SEC XBRL facts.

17 companies meet the strict same-year comparability rule. Click a bubble for the underlying fiscal year and filing source.

Financial facts ↗

Figure 3 · Manufacturing build-out

Nine tracked U.S. projects, with status kept explicit

City-level orientation only. A program can represent several announced facilities; cost is shown only when the cited source reports a comparable program value.

announced / plannedunder constructionoperational / rampingNumber = projects grouped within 90 km. Click a marker for the underlying records.Map geometry: U.S. Census Bureau 2024 cartographic boundaries ↗

Project	Status	Scope & announced products	Reported cost	Primary source
Peoria, Arizona	under-construction	advanced packaging and test campus advanced packaging · semiconductor test	$7.00B	Amkor Technology ↗
Chandler, Arizona	under-construction	two leading-edge logic fabs leading-edge logic · foundry capacity	Not reported	National Institute of Standards and Technology ↗
Boise, Idaho	under-construction	leading-edge memory fabs and R&D DRAM · advanced memory	Not reported	Micron Technology ↗
Clay, New York	planned	memory manufacturing campus leading-edge DRAM	$100.00B	National Institute of Standards and Technology ↗
West Lafayette, Indiana	planned	advanced packaging and R&D campus HBM advanced packaging	$3.87B	SK hynix ↗
Sherman, Texas	under-construction	analog and embedded semiconductor fab campus analog semiconductors · embedded processors	Not reported	National Institute of Standards and Technology ↗
Phoenix, Arizona	operational	leading-edge logic fab N4 logic wafers	Not reported	National Institute of Standards and Technology ↗
Phoenix, Arizona	under-construction	leading-edge logic fab N3 logic wafers	Not reported	National Institute of Standards and Technology ↗
Phoenix, Arizona	announced	three fabs, two advanced-packaging facilities, and R&D center advanced logic · advanced packaging	$100.00B	TSMC ↗

Figure 4 · Reported capital expenditure

Company-wide capex since 2017

Annual sum across covered issuers with a reported USD Company Facts value. The coverage set changes by year; this is not total industry capex.

$19.8B

2017

$31.0B

2018

$34.1B

2019

$30.3B

2020

$38.9B

2021

$50.0B

2022

$50.3B

2023

$48.8B

2024

$48.5B

2025

$2.5B

2026

Missing is not zero. Each bar sums only the 5–20 covered companies reporting in that year.

Open capex records ↗

What the evidence supports

Four legible conclusions, no hidden denominator

Reported project values and named dependencies are not market-share estimates.

Design is fabless; dependency is physical.

NVIDIA and AMD filings name external foundries, memory suppliers, and packaging processes behind their products.

17 disclosed edges ↗

Packaging has become strategic capacity.

SK hynix and Amkor announcements attach multibillion-dollar U.S. programs to HBM packaging and advanced assembly/test.

SK hynix source ↗

Leading-edge localization is a system build.

TSMC's announced U.S. expansion joins fabs, advanced packaging, and R&D rather than treating fabrication as a standalone asset.

TSMC source ↗

Data access

One snapshot, two interfaces

The page, versioned HTTP API, and read-only MCP tools resolve against the same bundled snapshot. IDs are stable strings; pagination is deterministic; no interface recomputes facts from a second store.

/api/semiconductors — coverage and dimensions
/api/semiconductors/snapshot — full immutable V1 capture
/api/semiconductors/explainers — eight sourced interactive layers
/api/semiconductors/companies · projects · financials
/api/semiconductors/relationships · sources · trade
MCP: search_semiconductor_intelligence · get_semiconductor_company · list_semiconductor_sources

Methodology & limits

Universe

54 current public companies selected for direct relevance across eight physical layers. Multiple membership is retained.

Financials

2017 onward, extracted from SEC Company Facts. Original unit, period, filing date, tag, source, and reported status are preserved.

Trade

V1 publishes a revision-labeled HTS heading codebook but no trade values. Headings 3818, 8486, 8541, and 8542 include products beyond advanced AI chips; an honest chart needs subheading concordance first.

Citation

MTS Intelligence, “The Supply Chain Behind Advanced AI Chips,” 2026-08-26, snapshot semiconductors-v1-9ec9a9512e4ae1d5.

Source register · evidence tier 1

Primary evidence used in V1

Our Technology In-Depth: Semiconductor Test ↗
Advantest · official-company
AMD fiscal 2025 Form 10-K ↗
U.S. Securities and Exchange Commission · regulatory
Amkor Technology Breaks Ground on New Semiconductor Advanced Packaging and Test Facility ↗
Amkor Technology · official-company
IC Semiconductor Test Services ↗
Amkor Technology · official-company
How Microchips Are Made ↗
ASML · official-company
Intel and ASML strengthen their collaboration to drive High-NA into manufacturing in 2025 ↗
ASML · official-company
Lithography Principles ↗
ASML · official-company
Broadcom fiscal 2024 annual report ↗
U.S. Securities and Exchange Commission · regulatory
Deposition Materials and Contamination Control ↗
Entegris · official-company
Chip Manufacturing 101: Process Control ↗
KLA · official-company
High-Bandwidth Memory (HBM) ↗
Micron Technology · official-company
Micron U.S. expansion ↗
Micron Technology · official-company
CHIPS for America Awards ↗
National Institute of Standards and Technology · government
Micron Technology Memory Chip Manufacturing Investment ↗
National Institute of Standards and Technology · government
Micron New York Semiconductor Manufacturing ↗
National Institute of Standards and Technology · government
TSMC Arizona Corporation ↗
National Institute of Standards and Technology · government
NVIDIA fiscal 2025 annual report ↗
U.S. Securities and Exchange Commission · regulatory
NVIDIA NVL72 AI Factory: System Hardware and Components ↗
NVIDIA · official-company
Qualcomm fiscal 2025 annual report ↗
U.S. Securities and Exchange Commission · regulatory
ADVANCED MICRO DEVICES INC SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
AMKOR TECHNOLOGY, INC. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
APPLIED MATERIALS INC /DE SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
ARM HOLDINGS PLC /UK SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
ASE Technology Holding Co., Ltd. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
ASML HOLDING NV SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
Broadcom Inc. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
CADENCE DESIGN SYSTEMS, INC. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
COHERENT CORP. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
DUPONT DE NEMOURS, INC. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
Entegris, Inc. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
GLOBALFOUNDRIES Inc. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
INTEL CORP SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
KLA CORP SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
LAM RESEARCH CORPORATION SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
Linde plc SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
Marvell Technology, Inc. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
MICROCHIP TECHNOLOGY INCORPORATED SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
Micron Technology, Inc. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
NVIDIA CORP SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
NXP Semiconductors N.V. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
ON SEMICONDUCTOR CORPORATION SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
QUALCOMM INC/DE SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
STMicroelectronics N.V. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
SYNOPSYS INC SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
TERADYNE, INC. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
TEXAS INSTRUMENTS INCORPORATED SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
TOWER SEMICONDUCTOR LTD. SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
Taiwan Semiconductor Manufacturing Company Limited SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
United Microelectronics Corporation SEC Company Facts ↗
U.S. Securities and Exchange Commission · regulatory
SK hynix Signs Investment Agreement for Advanced Chip Packaging with Indiana ↗
SK hynix · official-company
Silicon Wafer Production Processes ↗
SUMCO · official-company
What is Electronic Design Automation (EDA)? ↗
Synopsys · official-company
CoWoS Advanced Packaging Platform ↗
TSMC · official-company
Dedicated Foundry Services ↗
TSMC · official-company
High-Performance Computing Platform ↗
TSMC · official-company
TSMC Intends to Expand Its Investment in the United States to US$165 Billion ↗
TSMC · official-company
Harmonized Tariff Schedule of the United States ↗
U.S. International Trade Commission · official-standard

The Supply Chain Behind Advanced AI Chips

The accelerator is the visible object. The supply chain is the product.

Follow the accelerator from blueprint to qualified package

A chip is debugged in software before it becomes geometry.

Architecture + RTL

From RTL to a manufacturable layout

The accelerator is only useful when compute, memory, and fabric stay in balance.

Compute engines

GB300 NVL72: one design spans die, link, switch, and rack

Every patterned layer begins with materials clean enough not to become defects.

Single-crystal ingot

A polished wafer already contains a supply chain

A fab repeats deposition, patterning, etch, and measurement until a device emerges.

Deposition

One layer is a loop; a chip can repeat it up to 100 times

The foundry converts a design file into repeatable, qualified good die.

Tape-out + masks

TSMC Arizona Fab 1: operation is a state, not an announcement

HBM moves memory beside compute and widens the road between them.

DRAM dies

Micron HBM3E: bandwidth comes from width, proximity, and stacking

Advanced packaging is where compute, memory, power, heat, and yield meet.

Logic die + chiplets

CoWoS turns a package into a compute platform

Expensive dies create value only after assembly and test prove the complete device.

Wafer probe

Test is a loop from wafer to system—not a single pass/fail gate

Research intensity versus capital intensity

Nine tracked U.S. projects, with status kept explicit

Company-wide capex since 2017

Four legible conclusions, no hidden denominator

One snapshot, two interfaces

Universe

Financials

Trade

Citation

Primary evidence used in V1